With reference to FIG. 8, a conventional method for manufacturing a circuit device is described. Here, a description is given of a method for manufacturing a hybrid integrated circuit device in which a conductive pattern 108 and circuit elements are formed on a surface of a substrate 106 (refer, for example, to Patent Document 1 below).
Referring to FIG. 8A, first, solder 109 is formed at portions on a surface of the conductive pattern 108 formed on the surface of the substrate 106. The substrate 106 is for example a metallic substrate made of a metal such as aluminum, and is insulated from the conductive pattern 108 by an insulating layer 107. Pads 108A, pads 108B, and pads 108C are formed by the conductive pattern 108. In a later step, a heat sink is attached to an upper portion of each pad 108A. In a later step, a small-signal transistor is attached to each pad 108B. In a later step, a lead is attached to each pad 108C. Here, the solder 109 is formed on the surfaces of the relatively large pads 108A and the pads 108C.
Referring to FIG. 8B, next, a small-signal transistor 104C and a chip component 104B are attached with solder. In this step, heating is performed until the solder for connecting the transistor 104C and the like melts. Consequently, the solder 109 formed on the pads 108A and the pads 108C in the previous step also melt.
Referring to FIG. 8C, next, the small-signal transistor 104C is connected to predetermined portions of the conductive pattern 108 with thin wires 105B.
Referring to FIG. 9A, next, a heat sink 111 and a lead 101 are attached to each pad 108A and each pad 108C, respectively, by melting the solder 109 previously formed thereon. Here, the heat sink 111 has a power transistor 104A placed thereon, and is attached onto the pad 108A via the solder 109 previously formed. Then, the transistor 104A is connected to a desired portion of the conductive pattern 108 with a thick wire 105A.
Referring to FIG. 9B, a sealing resin 102 is formed to cover the circuit elements and the conductive pattern 108 formed on the surface of the substrate 106. With the steps above, a hybrid integrated circuit device 100 is manufactured.
Patent Document 1: Japanese Patent Application Publication No. 2002-134682